This invention relates to the use of multiple field programmable gate arrays (FPGAs) for emulating large circuit designs. In the production of semiconductor chips and systems, it is often desirable to test the circuit design by emulating the circuit design. Field programmable gate arrays allow for the emulation of a portion of a large circuit design. By connecting up a number of the FPGAs, larger circuit designs can be emulated.
One prior art circuit emulating system is described in Butts, et al. U.S. Pat. No. 5,036,473 entitled "Method of Using Electronically Reconfigurable Logic Circuits." A disadvantage of this prior art system is that it is difficult to easily upgrade to more powerful field programmable gate arrays when they become available from a vendor.
It is desired to have a system that easily upgrades to the use of more powerful field programmable gate arrays. Additionally, it is desirable to have a system that can switch among different types of field programmable gate arrays. It would be beneficial to have a system that would be able to support different types of field programmable gate arrays from different vendors.